The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same realizing high with stand voltage in an dielectric-isolated complementary bipolar transistor by provision of thickened collector region.
In recent years, a high with stand voltage and a high-degree of integration of transistors used in an audio amplifier, a display driver, etc. have been demanded. High degree of integration and high speed of a high withstand voltage (or high voltage) integrated circuit is preferably realized by the dielectric isolation technique in order to prevent a parasitic transistor from being formed and prevents a chip size from being increased owing to element isolation.
FIG. 13 shows a sectional view of a conventional typical semiconductor integrated circuit device (e.g. Japanese Patent Publication No. 11-354535). Now referring to FIGS. 14-20, an explanation will be given of a method for manufacturing the semiconductor integrated circuit device shown in FIG. 13.
FIG. 14 shows an area where a high voltage vertical NPN vertical transistor is to be formed and another area where a high voltage vertical PNP transistor is to be formed. First, a buried oxide film 2 having a thickness of about 2 xcexcm is formed on the surface of an N type substrate 3 of Si by thermal oxidation. The N type substrate is bonded to a supporting substrate 1 through the buried oxide film 2 at room temperature. The N type substrate 3 will be changed into an N+ type buried layer 4 and a P+ type buried layer 5, which are active layers, by the subsequent step. The N type substrate 3 may be a silicon substrate having e.g. resistivity of about 10 xcexa9xc2x7cm. Thereafter, the substrate 3 is annealed in an atmosphere of oxygen e.g. for about two hours at 1000xc2x0 C. to increase the bonding strength between the buried oxide film 2 and supporting substrate 1. Further, the thickness of the N type substrate 3 is reduced to a prescribed thickness, e.g. 2 xcexcm by e.g. mechanical polishing or chemical-mechanical polishing (CMP).
Next, ion implantation is executed in order to form an N+ buried layer 4. Specifically, by known photolithography, using as a mask photoresist (not shown) with an opening at an NPN transistor section, N type impurities of e.g. arsenic (As) are ion-implanted at an accelerating voltage of 50 keV and dose of 3xc3x971015/cm2. Thereafter, the photoresist is removed. Further ion-implantation is executed to form a P+ type buried layer 5. Specifically, by known photolithography, using as a mask photo resist (not shown) with an opening at a PNP transistor section, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 50 keV and dose of 3xc3x971015/cm2. Thereafter, the photoresist is removed.
Subsequently, the substrate is annealed in an atmosphere of water vapor e.g. for about one hour at 1100xc2x0 C. so that the arsenic introduced in the NPN transistor section and boron introduced in the PNP transistor section in the previous step are thermally diffused, respectively, thereby forming the N+ type buried layer 4 and the P+ type buried layer 5. In this annealing step, an oxide layer (not shown) is formed on the surface of the active layer. So, this oxide layer is removed by light etching using e.g. a hydrofluoric acid solution, which results in a structure as shown in FIG. 14.
Next, as shown in FIG. 15, an N type epitaxial layer 6 having resistively of 10 xcexa9xc2x7cm and a film thickness of 15 xcexcm is grown on the N+ type buried layer 4 and the P+ type buried layer 5 which are the active layers. The NPN transistor section of the N type epitaxial layer 6 constitutes an N type collector region 7, whereas the PNP transistor section of the N type epitaxial layer 6 is changed into a P type collector region 8 by the subsequent step. Specifically, an oxide film 9 having a thickness of 50 nm is formed by thermal oxidation. By known photolithography, using as a mask photoresist with an opening at a PNP transistor section, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 300 keV and dose of 8xc3x971012/cm2. The substrate is annealed in an atmosphere of inert gas for e.g. 7 (seven) hours at 1200xc2x0 C. to form the P type collector region 8 of the PNP transistor, which results in a structure as shown in FIG. 15.
By known photolithography, using as a mask photoresist with an opening on a base portion of the NPN transistor, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 40 keV and dose of 1xc3x971014/cm2. After the photoresist has been removed, by known photolithography, using as a mask photoresist with an opening on a base region of the PNP transistor, N type impurities of e.g. phosphorous (P) are ion-implanted at an accelerating voltage of 60 keV and dose of 1xc3x971014/cm2. After the photoresist has been removed, the substrate is annealed in an atmosphere of inert gas for e.g. 30 minutes at 900xc2x0 C. As a result, the impurities are thermally diffused to form a P type base region 10 of the NPN transistor and an N type base region 11 of the NPN transistor, respectively.
Next, by known photolithography, using as a mask photoresist with openings on an N type emitter region and an N type collector contact of the NPN transistor, N type impurities of e.g. arsenic (As) are ion-implanted at an accelerating voltage of 110 keV and dose of 5xc3x971015/cm2. Thereafter, the photoresist is removed. Subsequently, by known photolithography, using as a mask photoresist with openings on a P type emitter region and a P type collector contact of the PNP transistor, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 40 keV and dose of 3xc3x971015/cm2. After the photoresist has been removed, the substrate is annealed in an atmosphere of inert gas for e.g. about 30 minutes at 1000xc2x0 C. As a result, the impurities are thermally diffused to form an N+ type emitter region 12 and an N+ type collector contact 13 of the NPN transistor, and a P+ type emitter region 14 and P+ type collector contact of the PNP transistor, respectively. Thus, the structure as shown in FIG. 16 results.
Thereafter, the oxide layer 9, N type collector layer and N+ type buried layer 4 of the NPN transistor section are etched to reach the buried oxide layer 2, thereby forming a trench 16 for element isolation. Simultaneously, the oxide layer 9, P type collector layer 8 and P type buried layer 5 of the PNP transistor section are etched to reach the buried oxide layer 2, thereby forming a trench 16 for element isolation. The trenches 16 are formed so that the sides of the collector contacts 13 and 15 are exposed within the trenches 16, respectively. Thus, the structure as shown in FIG. 17 results.
Next, by e.g. thermal oxidation, an oxide film 17 having a thickness of about 500 nm is formed on the inner wall of the trench 16. Further, the oxide film 17 abutting on the collector contacts 13 and 15 of the NPN transistor and PNP transistor is removed by etching. Thus, the structure as shown in FIG. 18 results. By e.g. Chemical Vapor Deposition (CVD), poly-Si 18 is deposited to be buried within the trench 16 with the oxide film 17. Thereafter, the poly-Si 18 which has overflowed is etched back by Reactive Ion Etching (RIE) to flatten the substrate surface. Thus, the structure as shown in FIG. 19 results.
N type impurities are introduced into the poly-Si 18 buried in the trench 16 which abuts on the N+ type collector contact 13 of the NPN transistor. Specifically, by known photolithography, using as a mask photoresist with an opening at the trench, N type impurities of e.g. phosphorous (P) are ion-implanted at an accelerating voltage 180 keV and dose of 5xc3x971015/cm2. Further, P type impurities are introduced into the poly-Si 18 buried in the trench 16 which abuts on the P+ type collector contact 15 of the PNP transistor. Specifically, by known photolithography, using as a mask photoresist with an opening at the trench, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 180 keV and dose of 5xc3x971015/cm2.
Subsequently, the substrate is annealed in an atmosphere of inert gas for e.g. about 30 minutes at 1000xc2x0 C. As a result, the phosphorous (P) is thermally diffused from the trench of the NPN transistor, thereby forming an N+ type diffused layer 18n which connects the N+ type buried layer 4 and the N+ type collector contact 13. Simultaneously, boron (B) is thermally diffused from the trench of the PNP transistor, thereby forming a P+ type diffused layer 18p which connects the P+ buried layer 5 and the P+ type collector contact 15. Specifically, since the speed of diffusing the impurities in poly-Si is several tens of times as high as that in monocrystal Si, the impurities are diffused from the poly-Si within the trench into the monocrystal Si (epitaxial layer) of the collector region in a short time. The impurities which have moved into the collector region are diffused at the same speed as that in the monocrystal Si and accumulated in a layer at the interface between the trench and the collector region, thereby forming N+ type diffused layer 18n and the P+ type diffused layer 18p (collector walls). Thus, the structure as shown in FIG. 20 results.
Next, by e.g. CVD, an oxide film 19 is deposited on the entire surface of the substrate. Further, photoresist is deposited on the entire surface, and by known photolithography, openings are made at the positions where electrode are to be formed. Using the photoresist as a mask, by e.g. RIE, the openings are made in the oxide film 19 and the portions thereof where the electrodes are to be formed. By e.g. sputtering, aluminum (Al) 20 is deposited on the entire surface of the oxide film 19 with the openings at the portions where the electrodes are to be formed. Thereafter, photoresist is deposited on the entire surface, and by known photolithography, the photoresist is removed at the other portions than the portions where the electrodes are to be formed. Using the remaining photoresist as a mask, by e.g. RIE, the aluminum 20 is patterned. By removing the photoresist after the electrodes have been formed, the semiconductor device whose section is shown in FIG. 13 results.
In the semiconductor device having the structure as described above, the NPN transistor and PNP transistor which are adjacent to each other are electrically isolated by the dielectric isolation technique. Thus the degree of integration is enhanced, and the parasitic capacitance of the PN junction in each transistor can be reduced. This contribute to the high speed operation of the device. Further, in the semiconductor device having the structure as described above, the base-collector withstand voltage is assured by reducing the impurity concentration in the collector region 7, 8. However, reduction in the impurity concentration in the entire collector regions 7, 8 increases the series resistance of the collector, thus deteriorating the characteristic. In order to obviate such an inconvenience, under the lightly doped collector regions 7 and 8, the collector walls (N+ diffused layer 18n, P+ diffused layer 18p) are formed which connect the highly doped buried layers 4, 5 and the collector contacts 13, 15, respectively. In this way, the high with stand voltage of the bipolar transistor can be realized while the high speed operation which is a benefit of the bipolar transistor is utilized.
In the conventional semiconductor integrated circuit device, the lightly-doped collector regions 7 and 8, i.e. N type epitaxial layer 6 must be formed be thick in order to realize a high withstand voltage. In this case, in order to diffuse impurities from the surface of the N type epitaxial layer 6, heat treatment for a long time at a high temperature is required so that making the thick film of the collector regions has a limitation in process. Therefore, the film thickness of the collector regions formed of a single epitaxial layer has a limitation to realize the high with stand voltage. Accordingly, the conventional semiconductor integrated circuit could not provide a necessary withstand voltage.
In the conventional method of manufacturing a semiconductor integrated circuit device, in order to realize a dielectric-isolated complementary transistor pair composed of an NPN transistor and a vertical PNP transistor which are formed to be adjacent to each other on a single chip, a trench was used to isolate both transistors from each other. However, the trench has a limitation in depth and imperfection in an etching accuracy. Therefore, the conventional method has a problem that the etching for element isolation, attended with the thick film of the epitaxial layer for realizing the high withstand voltage, is difficult.
Where the lightly-doped collector regions 7 and 8, i.e. N type epitaxial layer 6 are made thick in order to realize the high withstand voltage, the lightly-doped collector region 8 of the vertical PNP transistor must be formed in such a manner that the ion-implanted impurities are heat treated for a long time at a high temperature. Therefore, the formation of the thick film of the N type epitaxial layer has a limitation in process, and increase the production cost. Further, ion-implanting at a high accelerating voltage and high dose for the purpose of increasing the depth of the impurity diffusion disadvantageously makes the crystal defect of the Si substrate remarkable.
The invention is carried out in view of the above-mentioned conventional problem. A method for manufacturing a semiconductor integrated circuit device comprising: a step of preparing one conductive semiconductor substrate; a step of forming plural opposite conductive epitaxial layers on said substrate, diffusing the one conductive and the opposite conductive buried layers formed on said substrate and said epitaxial layers to connect, and forming a first and second buried layers consisting of high concentration impurity diffusing layer at a first and second island regions and periphery of the first and second islands region; a step of etching the both end portions of said first and second island regions in V groove shape remaining said first and second buried layers, a step of forming an oxide film on the surface of said first and second buried layers and forming a polycrystal semiconductor layer on the oxide film; a step of forming an oxide film on said polycrystal semiconductor layer and bonding a supporting substrate through the oxide film; and a step of polishing said semiconductor substrate setting said supporting substrate to the bottom face till said first and second island regions are exposed.
In the method for manufacturing the semiconductor integrated circuit device according to the invention, it is characterized in that process etching said first and second island regions is suitably a process etching in V groove in order to remove completely the border face between said buried layer consisting of low concentration impurity diffusing layer forming said first and second island regions and said epitaxial layer, to etch completely to the bottom portion of said first and second island regions made thick in film, and to realize dielectric-isolated complementary bipolar transistors.
In the method for manufacturing the semiconductor integrated circuit device according to the invention, the buried layer comprising high concentration impurity diffusing layer formed at periphery of the collector region is suitably formed at the same time forming the buried layer forming the collector region, and along inclined lines of V groove etching. Thus, high concentration buried layer too is formed at the same time by process of V groove etching isolating elements between said first and second island regions so as to shorten manufacturing process of the semiconductor integrated circuit device.
In the method for manufacturing the semiconductor integrated circuit device according to the invention, generation of crystal defect at the substrate can be clearly decreased comparing with a forming collector taking-out diffusion layer ion-injecting on surface of the substrate because ion injection is carried out on surface of the epitaxial layer.